1. Field of the Invention
The present invention is generally directed to the field of semiconductor processing, and, more particularly, to a method of preventing or reducing delamination of insulating layers formed on an integrated circuit device.
2. Description of the Related Art
Many modern integrated circuit devices are very densely packed, i.e., there is very little space between the transistors formed above the substrate. Thus, conductive interconnections used to electrically interconnect the transistors on an integrated circuit device are made in multiple layers to conserve plot space on the semiconducting substrate. By way of background, a portion of an illustrative integrated circuit device 10 formed above a semiconducting substrate 12 is depicted in FIG. 1. The integrated circuit device 10 is comprised of a plurality of transistors 14 formed between shallow trench isolation (STI) regions 15.
The integrated circuit device 10 further comprises a plurality of conductive interconnections, i.e., conductive lines 16 and conductive plugs 18, formed in layers 22, 20, respectively, of insulating material. As is readily apparent to those skilled in the art, the conductive plugs are means by which various layers of conductive lines, and/or semiconductor devices, may be electrically coupled to one another. The conductive lines and plugs may be made of a variety of conductive materials, such as copper, aluminum, aluminum alloys, titanium, tantalum, titanium nitride, tantalum nitride, tungsten, etc. Within the semiconductor industry, conductive plugs that connect conductive lines are sometimes referred to as xe2x80x9cvias,xe2x80x9d whereas conductive plugs that contact a portion of a transistor are sometimes referred to as xe2x80x9ccontacts.xe2x80x9d Thus, the term plug as used herein should be understood to refer to both contacts and vias.
The illustrative transistor 14 shown in FIG. 1 is generally comprised of a gate insulation layer 13, a gate electrode 17, a sidewall spacer 19 positioned adjacent the gate electrode 17, and a plurality of source/drain regions 21. The gate insulation layer 13 may be formed from a variety of materials, such as silicon dioxide. The gate electrode 17 may also be formed from a variety of materials, such as a doped polycrystalline silicon (polysilicon). The source and drain regions 21 may be formed by performing one or more ion implantation processes in which a dopant material is implanted into the substrate 12.
One illustrative process flow for forming the above-referenced structure will now be described with reference to the formation of the conductive lines 16 above the conductive plugs 18 in the insulating layer 20. Initially, a layer of conductive material (not shown), e.g., aluminum, is formed above the surface 23 of the insulating layer 20. Thereafter, the conductive lines 16 are formed by patterning the layer of conductive material using known photolithography and etching processes. Next, a layer of insulating material 22 is formed between the conductive lines 16. This insulating material 22 may be comprised of a variety of materials, such as silicon dioxide, silicon oxynitride, a tri-methyl silicate product known as Black Diamond or 3MS (sold respectively by Applied Materials and Novellus), and it may be formed by a variety of techniques, e.g., high density plasma (HDP) deposition, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), etc.
Given the very small spacing between the conductive lines 16 in some modem integrated circuit devices, the layer of insulating material 22 may be comprised of silicon dioxide that is formed by an HDP process. Such layers are typically formed using a recipe comprised of oxygen, silane and argon. Thereafter, one or more chemical mechanical polishing (CMP) operations are performed to remove excess amounts of the insulating layer 22 from above the surface 17 of the conductive lines 16. That is, CMP operations are performed until such time as the surface 25 of the insulating layer 22 and the surface 17 of the conductive lines 16 are approximately co-planar.
FIG. 2 is a top view of an illustrative wafer 24. The wafer 24 is comprised of an active region 26 and an edge region 27. A plurality of die 28 are formed in the active region 26 of the wafer 24 above the substrate 12. FIG. 3 is a side view of a portion of the device shown in FIG. 2. Generally, semiconductor devices are manufactured by forming a number of layers or films of material above a semiconductor substrate, such as the insulating layers 20 and 22 described above, and patterning or otherwise processing these layers or films to form the desired electrical devices, e.g., transistors, capacitors, etc. However, there are many irregularities and defects that exist on or near the edge region 27 of the wafer.
For example, problems have arisen in situations when the insulating layers 20, 22 described above are comprised of silicon dioxide formed by an HDP process. In particular, during the formation of the insulating layers 20, 22 between the conductive lines 16, the insulating layers 20, 22 are also formed above the edge region 27 of the wafer 24 where integrated circuit devices are not formed. This edge region 27 of the wafer 24 tends to be problematic in that, since integrated circuit devices are not formed in this region, it is not subjected to the same processing operations as compared to other areas of the wafer 24 where integrated circuit devices are formed. For example, CMP operations focus on proper planarization of the active region 26 of the wafer 24 where devices are formed, and the edge region 27 may only by contacted on an infrequent or irregular basis.
With respect to the situation where the insulating layers 20, 22 are comprised of a silicon dioxide HDP layer as described above, delamination and other defects of the insulating layers 20, 22 on the edge region 27 of the wafer 24 have been observed. More particularly, portions of the insulating layers 20, 22 have tended to spall or pop off and land in the active region 26 of the wafer 24. Such defects can have severe adverse consequences on the device performance. For example, a delaminated flake from a silicon dioxide (HDP) layer may become embedded in a subsequently deposited layer of insulating material. Thereafter, subsequent chemical mechanical polishing operations may rip the flake out of the deposited layer of insulating material, leaving a hole or recess in the layer of insulating material. Subsequent processes performed to form the conductive interconnection for the device, e.g., barrier metal layer deposition, tungsten deposition, and tungsten CMP, may result in a metal, e.g., tungsten, being positioned in the opening or recess in the insulating layer, and such defects may lead to the formation of short circuits in the completed device.
The present invention is directed to a method of solving or at least reducing some or all of the aforementioned problems.
The present invention is general directed to a method of reducing or preventing delaminations or other defects in layers of insulating materials. In one embodiment, the method comprises forming a layer of silicon dioxide by providing a semiconducting substrate, positioning the substrate in a high density plasma process chamber, and forming a layer of silicon dioxide above the substrate using a high density plasma process comprised of an oxygen/silane flowrate ratio that is less than or equal to 0.625. In other illustrative embodiments, an oxygen/silane flowrate ratio ranging from approximately 0.333-0.625 may be used.
In another illustrative embodiment, the method comprises providing a semiconducting substrate having a partially formed integrated circuit device formed thereabove, the integrated circuit device having a plurality of conductive interconnections, e.g., conductive lines or conductive plugs, formed thereon, and positioning the substrate in a high density plasma process chamber. The method further comprises forming a first layer of silicon dioxide between the plurality of conductive interconnections using a high density plasma process comprised of an oxygen/silane flowrate ratio ranging from approximately 0.333-0.625, and forming a layer of insulating material above the first layer between the conductive interconnections.
In another aspect of the present invention, an integrated circuit device is provided. In one illustrative embodiment, the device is comprised of a plurality of conductive interconnections, e.g., conductive lines, formed above a semiconducting substrate, a layer of silicon dioxide having a silicon content ranging from approximately 50-75 weight percent positioned between the conductive interconnections, and a layer of insulating material positioned above the layer of silicon dioxide between the conductive interconnections.